Recent years have witnessed widespread use of electronic devices such as personal computers and PDAs (personal digital assistants) containing a plurality of LSIs (large-scale integrated circuits) in their system configuration. The signals used by these LSIs are input, output, and processed using synchronizing clock signals. Generally, a device that operates on a synchronizing clock signal is structured so that the speed of its performance is proportional to the frequency of the clock signal. Typical devices operating on the synchronizing clock signal include CPUs (Central Processing Units), memories, and north bridges.
Also known today are devices acting on variable, not fixed operating frequencies. Many electronic devices such as personal computers, PDAs and cellular phones are designed to operate only as needed. In more and more systems, their operating frequency is lowered in standby mode or in sleep mode in order to attain a reduced level of power dissipation; when a call is being made or moving picture signals are being processed, the operating frequency is raised to accelerate the processing of the systems. (One such system is disclosed illustratively in Japanese Patent Laid-open No. 2000-163965.)
These systems with their operating frequencies made variable usually have their functional parts divided in two regions. One region for which the operating frequency must remain fixed is isolated from the other region fed with a clock signal at variable frequencies. This structure is intended to prevent the region of the parts operating at variable frequencies from adversely affecting the other region of fixed-frequency parts.
Meanwhile, the information processing apparatuses using a synchronizing signal at varied frequencies are required to provide steady performance regardless of their synchronizing signal being fixed or variable. Generally, if an apparatus is guaranteed to operate at a high frequency, i.e., at short clock intervals, the apparatus will also operate at reduced frequencies but the performance of its signal processing will be lowered in proportion to the drop in frequency. Although the dissipation of power is curtailed by simply reducing the operating speed in keeping with the lowered clock frequency, that is not an optimally controlled operating state. A more sophisticated control scheme has been called for.
The present invention has been made in view of the aforementioned technical problems and provides an information processing apparatus, an information storing apparatus, an information processing method, and an information processing program for implementing an optimal signal processing setup that ensures steady performance using variable operating frequencies.